Datasheet
V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 1327 of 1513
Aug 12, 2011
Table 25-11. Operation After Releasing Sub-IDLE Mode by Interrupt Request Signal
Release Source Interrupt Enabled (EI) Status Interrupt Disabled (DI) Status
Non-maskable interrupt request
signal
Execution branches to the handler address.
Maskable interrupt request signal
Execution branches to the handler address
or the next instruction is executed.
The next instruction is executed.
(2) Releasing sub-IDLE mode by reset
The same operation as the normal reset operation is performed.
Table 25-12. Operating Status in Sub-IDLE Mode
Operating Status Setting of Sub-IDLE Mode
Item
When Main Clock Is Oscillating When Main Clock Is Stopped
Subclock oscillator (fXT) Oscillation enabled
Internal oscillator (fR) Oscillation enabled
PLL Operable Stops operation
Note 1
CPU Stops operation
DMA controller Stops operation
Interrupt controller Stops operation
TAA0 to TAA5 Stops operation
TAB0, TAB1 Stops operation
TMM0 to TMM3 Operable when fR/8 or fXT is selected as the count clock
Timer
TMT0 Stops operation
Real-time counter (RTC) Operable Operable when fXT is selected as the
count clock
Watchdog timer (WDT2) Operable when fR or fXT is selected as the count clock
CSIF0 to CSIF4 Operable when the SCKFn input clock is selected as the count clock (n = 0 to 4)
I
2
C00 to I
2
C02 Stops operation
Serial interface
UARTC0 to UARTC4 Stops operation (but UARTC0 is operable when the ASCKC0 input clock is selected)
A/D converter Holds operation (conversion result held)
Note 2
D/A converter Holds operation (output held
Note 2
)
Real-time output function (RTO) Stops operation (output held)
Key interrupt function (KR) Operable
CRC operation circuit Stops operation
External bus interface See CHAPTER 5 BUS CONTROL FUNCTION. (same operation status as IDLE
mode).
Port function Retains status before sub-IDLE mode was set
Internal data The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before the sub-IDLE mode was set.
CAN
Note 3
Stops operation
USB function Stops operation
Notes 1. Be sure to stop the PLL (PLLCTL.PLLON bit = 0) before stopping the main clock.
2. To realize low power consumption, stop the A/D and D/A converters before shifting to the sub-IDLE mode.
3.
μ
PD70F3770, 70F3771 only