Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 1316 of 1513
Aug 12, 2011
25.5 IDLE2 Mode
25.5.1 Setting and operation status
The IDLE2 mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 10 and setting the PSC.STP bit to 1 in the
normal operation mode.
In the IDLE2 mode, the clock oscillator continues operation but clock supply to the CPU, PLL, flash memory, and other
on-chip peripheral functions stops.
As a result, program execution stops and the contents of the internal RAM before the IDLE2 mode was set are retained.
The CPU, PLL, and other on-chip peripheral functions stop operating. However, the on-chip peripheral functions that can
operate with the subclock or an external clock continue operating.
Table 25-7 shows the operating status in the IDLE2 mode.
The IDLE2 mode can reduce the power consumption more than the IDLE1 mode because it stops the operations of the
on-chip peripheral functions, PLL, and flash memory. However, because the PLL and flash memory are stopped, a setup
time for the PLL and flash memory is required when IDLE2 mode is released.
Cautions 1. Insert five or more NOP instructions after the instruction that stores data in the PSC register to
set the IDLE2 mode.
2. If the IDLE2 mode is set while an unmasked interrupt request signal is being held pending, the
IDLE2 mode is released immediately by the pending interrupt request.