Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 1313 of 1513
Aug 12, 2011
25.4 IDLE1 Mode
25.4.1 Setting and operation status
The IDLE1 mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 00 and setting the PSC.STP bit to 1 in the
normal operation mode.
In the IDLE1 mode, the clock oscillator, PLL, and flash memory continue operating but clock supply to the CPU and
other on-chip peripheral functions stops.
As a result, program execution stops and the contents of the internal RAM before the IDLE1 mode was set are retained.
The CPU and other on-chip peripheral functions stop operating. However, the on-chip peripheral functions that can
operate with the subclock or an external clock continue operating.
Table 25-5 shows the operating status in the IDLE1 mode.
The IDLE1 mode can reduce the power consumption more than the HALT mode because it stops the operation of the
on-chip peripheral functions. The main clock oscillator does not stop, so the normal operation mode can be restored
without waiting for the oscillation stabilization time after the IDLE1 mode has been released, in the same manner as when
the HALT mode is released.
Cautions 1. Insert five or more NOP instructions after the instruction that stores data in the PSC register to
set the IDLE1 mode.
2. If the IDLE1 mode is set while an unmasked interrupt request signal is being held pending, the
IDLE1 mode is released immediately by the pending interrupt request.