Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 1312 of 1513
Aug 12, 2011
(2) Releasing HALT mode by reset
The same operation as the normal reset operation is performed.
Table 25-3. Operating Status in HALT Mode
Operating Status Setting of HALT Mode
Item
When Subclock Is Not Used When Subclock Is Used
Main clock oscillator (fX) Oscillation enabled
Subclock oscillator (fXT)
−
Oscillation enabled
Internal oscillator (fR) Oscillation enabled
PLL Operable
CPU Stops operation
DMA controller Operable
Interrupt controller Operable
TAA0 to TAA5 Operable
TAB0, TAB1 Operable
TMM0 to TMM3
Operable when a clock other than f
XT is
selected as the count clock
Operable
Timer
TMT0 Operable
Real-time counter (RTC)
Operable when f
X (divided BRG) is
selected as the count clock
Operable
Watchdog timer (WDT2)
Operable when a clock other than f
XT is
selected as the count clock
Operable
CSIF0 to CSIF4 Operable
I
2
C00 to I
2
C02 Operable
Serial interface
UARTC0 to UARTC4 Operable
A/D converter Operable
D/A converter Operable
Real-time output function (RTO) Operable
Key interrupt function (KR) Operable
CRC operation circuit Operable (No data input to the CRCIN register because the CPU is stopped)
External bus interface See CHAPTER 5 BUS CONTROL FUNCTION.
Port function Retains status before HALT mode was set
Internal data
The CPU registers, statuses, data, and all other internal data such as the contents of
the internal RAM are retained as they were before the HALT mode was set.
CAN
Note
Operable
USB function Operable
Note
μ PD70F3770, 70F3771 only