Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 1310 of 1513
Aug 12, 2011
(3) Oscillation stabilization time select register (OSTS)
The wait time until the oscillation stabilizes after the STOP mode is released or the wait time until the on-chip flash
memory stabilizes after the IDLE2 mode is released is controlled by the OSTS register.
This register can be read or written in 8-bit units.
Reset sets this register to 06H.
0OSTS 0 0 0 0 OSTS2 OSTS1 OSTS0
OSTS2
0
0
0
0
1
1
1
1
Selection of oscillation stabilization time/setup time
Note
OSTS1
0
0
1
1
0
0
1
1
OSTS0
0
1
0
1
0
1
0
1
After reset: 06H R/W Address: FFFFF6C0H
2
10
/fX
2
11
/fX
2
12
/fX
2
13
/fX
2
14
/fX
2
15
/fX
2
16
/fX
3 MHz
0.341 ms
0.683 ms
1.365 ms
2.730 ms
5.461 ms
10.923 ms
21.85 ms
6 MHz
0.171 ms
0.341 ms
0.683 ms
1.365 ms
2.731 ms
5.461 ms
10.92 ms
f
X
Setting prohibited
Note The oscillation stabilization time and setup time are required when the STOP mode and
IDLE2 mode are released, respectively.
Cautions 1. The wait time following release of the STOP mode does not include the time
until the clock oscillation starts ("a" in the figure below) following release of
the STOP mode, regardless of whether the STOP mode is released by reset or
the occurrence of an interrupt request signal.
a
STOP mode release
Voltage waveform of X1 pin
V
SS
2. Be sure to set bits 3 to 7 to “0”.
3. The oscillation stabilization time following reset release is 2
16
/fX (because the
initial value of the OSTS register = 06H).
Remark f
X = Main clock oscillation frequency