Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 32-Bit 48 MHz I/O number 77

1301

V850ES/JG3-H, V850ES/JH3-H CHAPTER 25 STANDBY FUNCTION

R01UH0042EJ0500 Rev.5.00 Page 1307 of 1513

Aug 12, 2011

Figure 25-1. Status Transition

Reset

Subclock operation mode

(fx operates, PLL operates)

Subclock operation mode

(fx stops, PLL stops)

Sub-IDLE mode

(fx operates, PLL operates)

Sub-IDLE mode

(fx stops, PLL stops)

STOP mode

(fx stops, PLL stops)

IDLE2 mode

(fx operates, PLL stops)

IDLE1 mode

(fx operates, PLL operates)

IDLE1 mode

(fx operates, PLL stops)

HALT mode

(fx operates, PLL stops)

HALT mode

(fx operates, PLL operates)

Normal operation mode

Oscillation

stabilization wait

Clock through mode

(PLL operates)

Clock through mode

(PLL stops)

PLL mode

(PLL operates)

Internal oscillation

clock operation

WDT overflow

Oscillation

stabilization wait

Note

PLL lockup

time wait

Oscillation

stabilization wait

Note

Oscillation

stabilization wait

Note

Note If a WDT overflow occurs during an oscillation stabilization time, the CPU operates on the internal

oscillation clock.

Remark f

X: Main clock oscillation frequency