Datasheet
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 1301 of 1513
Aug 12, 2011
(7) Noise elimination control register (INTNFC)
Analog noise elimination and digital noise elimination can be selected for the INTP02 pin. The noise elimination
settings are performed using the INTNFC register.
When analog noise elimination is selected, the input level of the pin is detected as an edge by maintaining it for a
specific time or longer.
When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among
f
XX/64, fXX/128, fXX/256, fXX/512, fXX/1,024, and fXT. Sampling is performed 3 times.
Even when digital noise elimination is selected, using fXT as the sampling clock makes it possible to use the INTP02
interrupt request signal to release the IDLE1, IDLE2, and STOP modes.
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
Caution After the sampling clock has been changed, it takes 3 sampling clocks to initialize the digital
noise eliminator. Therefore, if an INTP02 valid edge is input within these 3 sampling clocks after
the sampling clock has been changed, an interrupt request signal may be generated. Therefore,
be careful about the following points when using the interrupt and DMA functions.
• When using the interrupt function, after the 3 sampling clocks have elapsed, enable interrupts
after the interrupt request flag (PIC2.PIF2 bit) has been cleared.
• When using the DMA function (started by INTP02), enable DMA after 3 sampling clocks have
elapsed.
INTNFENINTNFC 0 0 0 0 INTNFC2 INTNFC1 INTNFC0
f
XX
/64
f
XX
/128
f
XX
/256
f
XX
/512
f
XX
/1,024
f
XT
(subclock)
INTNFC2
0
0
0
0
1
1
Digital sampling clock
Setting prohibited
INTNFC1
0
0
1
1
0
0
INTNFC0
0
1
0
1
0
1
After reset: 00H R/W Address: FFFFF728H
Analog noise elimination (60 ns (TYP.))
Digital noise elimination
INTNFEN
0
1
Settings of INTP02 pin noise elimination
Other than above
Remarks 1. Since sampling is performed 3 times, the reliably eliminated noise width is 2 sampling clocks.
2. In the case of noise with a width smaller than 2 sampling clocks, an interrupt request signal is
generated if noise synchronized with the sampling clock is input.