Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 1295 of 1513
Aug 12, 2011
(1) External interrupt falling, rising edge specification register 0 (INTF0, INTR0)
The INTF0 and INTR0 registers are 8-bit registers that specify detection of the falling and rising edges of the NMI
pin via bit 2 and the external interrupt pins (INTP00 to INTP04) via bits 0, 1, 3 to 5.
These registers can be read or written in 8-bit or 1-bit units.
Reset sets these registers to 00H.
Caution When the function is changed from the external interrupt function (alternate function) to the port
function, an edge may be detected. Therefore, set the INTF0n and INTR0n bits to 00, and then set
the port mode.
0INTF0 0 INTF05 INTF04 INTF03 INTF02
NMI INTP01 INTP00
INTF01
Note
INTF00
Note
After reset: 00H R/W Address: INTF0 FFFFFC00H, INTR0 FFFFFC20H
0INTR0 0 INTR05 INTR04 INTR03 INTR02 INTR01
Note
INTR00
Note
INTP02INTP03INTP04
NMIINTP02 INTP01 INTP00INTP03INTP04
76543210
76543210
Note V850ES/JH3-H only
Remark For how to specify a valid edge, see Table 23-5.
Table 23-5. Valid Edge Specification
INTF0n INTR0n Valid Edge Specification (n = 0 to 5)
0 0 No edge detected
0 1 Rising edge
1 0 Falling edge
1 1 Both rising and falling edges
Caution Be sure to set the INTF0n and INTR0n bits to 00 when these registers are not used as the NMI or
INTP00 to INTP04 pins.
Remark n = 0, 1: Control of INTP00 and INTP01 pins
n = 2: Control of NMI pin
n = 3 to 5: Control of INTP02 to INTP04 pins