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ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 32-Bit 48 MHz I/O number 77
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V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 1293 of 1513
Aug 12, 2011
(2) Restoration
Restoration from a debug trap is executed with the DBRET instruction.
With the DBRET instruction, the CPU performs the following steps and transfers control to the address of the
restored PC.
<1> The restored PC and PSW are read from DBPC and DBPSW.
<2> Control is transferred to the fetched address of the restored PC and PSW.
Caution DBPC and DBPSW can be accessed only during the interval between the execution of the
DBTRAP instruction and DBRET instruction.
The processing format for restoration from a debug trap is shown below.
Figure 23-14. Processing Format of Restoration from Debug Trap
DBRET instruction
PC
PSW
DBPC
DBPSW
Jump to address of restored PC