Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 1290 of 1513
Aug 12, 2011
23.5 Exception Trap
An exception trap is an interrupt that is requested when the illegal execution of an instruction takes place. In the
V850ES/JG3-H and V850ES/JH3-H, an illegal opcode exception (ILGOP: Illegal Opcode Trap) is considered as an
exception trap.
23.5.1 Illegal opcode
An illegal opcode is defined as an instruction with instruction opcode (bits 10 to 5) = 111111B, sub-opcode (bits 26 to
23) = 0111B to 1111B, and sub-opcode (bit 16) = 0B. When such an instruction is executed, an exception trap is
generated.
15 1623 22
××××××0××××××××××111111×××××
27 26310451011
1
1
1
1
1
1
0
1
to
×: Arbitrary
Caution It is recommended not to use an illegal opcode because instructions may newly be assigned in the
future.
(1) Operation
If an exception trap occurs, the CPU performs the following processing, and transfers control to the handler
routine.
<1> Saves the restored PC to DBPC.
<2> Saves the current PSW to DBPSW.
<3> Sets the PSW.NP, PSW.EP, and PSW.ID bits to 1.
<4> Sets the handler address (00000060H) corresponding to the exception trap to the PC, and transfers control.
The processing of the exception trap is shown below.