Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION

R01UH0042EJ0500 Rev.5.00 Page 1287 of 1513

Aug 12, 2011

23.4 Software Exception

A software exception is generated when the CPU executes the TRAP instruction, and can always be acknowledged.

23.4.1 Operation

If a software exception occurs, the CPU performs the following processing, and transfers control to the handler routine.

<1> Saves the restored PC to EIPC.

<2> Saves the current PSW to EIPSW.

<3> Writes an exception code to the lower 16 bits (EICC) of ECR (interrupt source).

<4> Sets the PSW.EP and PSW.ID bits to 1.

<5> Sets the handler address (00000040H or 00000050H) corresponding to the software exception to the PC, and

transfers control.

The processing of a software exception is shown below.

Figure 23-9. Software Exception Processing

TRAP instruction

EIPC

EIPSW

ECR.EICC

PSW.EP

PSW.ID

Restored PC

PSW

Exception code

Handler address

CPU processing

Exception processing

Note

Note TRAP instruction format: TRAP vector (the vector is a value from 00H to 1FH.)

The handler address is determined by the TRAP instruction’s operand (vector). If the vector is 00H to 0FH, it becomes

00000040H, and if the vector is 10H to 1FH, it becomes 00000050H.