Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 1284 of 1513
Aug 12, 2011
(2/2)
PMK14
PMK06
Note 2
IMR0 (IMR0H
Note 1
) PMK13
PMK05
PMK12
PMK04
Note 2
PMK11
PMK03
Note 2
PMK10
PMK02
PMK09
PMK01
Note 2
PMK08
PMK00
Note 2
PMK07
LVIMK
After reset: FFFFH R/W Address: IMR0 FFFFF100H,
After reset: FFFFH R/W Address: IMR1 FFFFF102H,
After reset: FFFFH R/W Address: IMR2 FFFFF104H,
TT0CCMK0
TAB0CCMK2
IMR1 (IMR1H
Note 1
) TT0OVMK
TAB0CCMK1
TAB1CCMK3
TAB0CCMK0
TAB1CCMK2
TAB0OVMK
TAB1CCMK1
PMK18
TAB1CCMK0
PMK17
TAB1OVMK
PMK16
TAB0CCMK3
PMK15
TAA4CCMK0
TAA1CCMK1
TAA2OVMK
TMT0CCMK1
xxMKn
0
1
Interrupt servicing enabled
Interrupt servicing disabled
IMR2 (IMR2H
Note 1
) TAA4OVMK
TAA1CCMK0 TAA1OVMK
TAA3CCMK0
TAA0CCMK1 TAA0CCMK0
TAA0OVMK
TAA2CCMK1TAA3CCMK1 TAA3OVMK TAA2CCMK0
TMTIECMK
89101112131415
1234567 0
IMR2L
IMR1L
IMR0L
89101112131415
1234567 0
89101112
Setting of interrupt mask flag
14 1315
1234567 0
IMR2L FFFFF104H, IMR2H FFFFF105H
IMR1L FFFFF102H, IMR1H FFFFF103H
IMR0L FFFFF100H, IMR0H FFFFF101H
Notes 1. To read bits 8 to 15 of the IMR0 to IMR2 registers in 8-bit or 1-bit units, specify them as bits 0 to 7 of
IMR0H to IMR2H registers.
2. V850ES/JH3-H only
Remark xx: Identification name of each peripheral unit (see Table 23-4 Interrupt Control Register
(xxICn)).
n: Peripheral unit number (see Table 23-4 Interrupt Control Register (xxICn))