Datasheet
V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 1283 of 1513
Aug 12, 2011
23.3.5 Interrupt mask registers 0 to 5 (IMR0 to IMR5)
The IMR0 to IMR5 registers set the interrupt mask state for the maskable interrupts. The xxMKn bit of the IMR0 to
IMR5 registers is equivalent to the xxICn.xxMKn bit.
The IMRm register can be read or written in 16-bit units.
If the higher 8 bits of the IMRm register are used as an IMRmH register and the lower 8 bits as an IMRmL register,
these registers can be read or written in 8-bit or 1-bit units (m = 0 to 5).
Reset sets these registers to FFFFH.
Caution The device file defines the xxICn.xxMKn bit as a reserved word. If a bit is manipulated using the
name of xxMKn, the contents of the xxICn register, instead of the IMRm register, are rewritten (as a
result, the contents of the IMRm register are also rewritten).
(1/2)
CF3TMK
TM3EQMK0
IMR3 (IMR3H
Note 1
) CF3RMK
TM2EQMK0
CF2TMK
TM1EQMK0
CF2RMK
TM0EQMK0
CF1TMK
TAA5CCMK1
CF1RMK
TAA5CCMK0
CF0TMK
TAA5OVMK
After reset: FFFFH R/W Address: IMR3 FFFFF106H,
After reset: FFFFH R/W Address: IMR4 FFFFF108H,
After reset: FFFFH R/W Address: IMR5 FFFFF10AH,
DMAMK2
UC2TMK
IMR4 (IMR4H
Note 1
) DMAMK1
UC2RMK
DMAMK0
UC1TMK
ADMK UC4TMK
UC0TMK
UC4RMK
UC0RMK
UC3TMK
CF3TMK CF3RMK
1
DMAMK3
IMR5 (IMR5H
Note 1
) 1 UFMK0
RTC2MK RTC1MK RTC0MK
1UFMK1 1 1
KRMK
89101112131415
1234567 0
IMR5L
IMR4L
IMR3L
89101112131415
1234567 0
8910111214 13
15
1234567 0
IMR5L FFFFF10AH, IMR5H FFFFF10BH
IMR4L FFFFF108H, IMR4H FFFFF109H
IMR3L FFFFF106H, IMR3H FFFFF107H
TAA4CCMK1
CF0RMK/
IICMK1
UC3RMK/
IICMK0
UC1RMK/
IICMK2
ERRMK0
Note 2
WUPMK0
Note 2
RECMK0
Note 2
TRXMK0
Note 2
Notes 1. To read bits 8 to 15 of the IMR3 to IMR5 registers in 8-bit or 1-bit units, specify them as bits 0 to 7 of
IMR3H to IMR5H registers.
2.
μ
PD70F3770, 70F3771 only
Caution Set bits 9 to 11, 14, 15 of the IMR5 register to 1. If the setting of these bits is changed, the
operation is not guaranteed.
Remark xx: Identification name of each peripheral unit (see Table 23-4 Interrupt Control Register
(xxICn)).
n: Peripheral unit number (see Table 23-4 Interrupt Control Register (xxICn))