Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 23 INTERRUPT/EXCEPTION PROCESSING FUNCTION
R01UH0042EJ0500 Rev.5.00 Page 1274 of 1513
Aug 12, 2011
23.3.2 Restore
Recovery from maskable interrupt servicing is carried out by the RETI instruction.
When the RETI instruction is executed, the CPU performs the following processing, and transfers control to the address
of the restored PC.
<1> Loads the restored PC and PSW from EIPC and EIPSW because the PSW.EP bit is 0 and the PSW.NP bit is 0.
<2> Transfers control back to the address of the restored PC and PSW.
The processing of the RETI instruction is shown below.
Figure 23-6. RETI Instruction Processing
PSW.EP
RETI instruction
PSW.NP
Restores original processing
1
1
0
0
PC
PSW
Corresponding
bit of ISPR
Note
EIPC
EIPSW
0
PC
PSW
FEPC
FEPSW
Note For the ISPR register, see 23.3.6 In-service priority register (ISPR).
Caution When the EP and NP bits are changed by the LDSR instruction during maskable interrupt
servicing, in order to restore the PC and PSW correctly during recovery by the RETI
instruction, it is necessary to set the EP bit back to 0 and the NP bit back to 0 using the LDSR
instruction immediately before the RETI instruction.
Remark The solid line shows the CPU processing flow.