Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 4 PORT FUNCTIONS
R01UH0042EJ0500 Rev.5.00 Page 126 of 1513
Aug 12, 2011
4.3.6 Port 5
Port 5 is 6-bit (V850ES/JG3-H)/2-bit (V850ES/JH3-H) port that controls I/O in 1-bit units.
Port 5 includes the following alternate-function pins.
Table 4-11. Port 5 Alternate-Function Pins
Pin No. Pin Name
V850ES/
JG3-H
V850ES/
JH3-H
Alternate-Function Pin Name I/O Remark
P50 35 47
TIAB01/KR0/TOAB01/RTP00
/UDMARQ1
I/O
P51 36 48
TIAB02/KR1/TOAB02/RTP01
/UDMAAK1
I/O
P52 37
−
TIAB03/KR2/TOAB13/RTP02
/DDI
Note
I/O
P53 38
−
SIF2/TIAB00/KR3/TOAB10
/RTP03/DDO
Note
I/O
P54 39
−
SOF2/KR4/RTP04/DCK
Note
I/O
P55 40
−
SCKF2/KR5/RTP05/DMS
Note
I/O
P56 41
−
INTP05/DRST
Note
Input
Selectable as N-ch open-drain output
Note The DDI, DDO, DCK, DMS, and DRST pins are used for on-chip debugging.
If on-chip debugging is not used, fix the P05/INTP02/DRST pin to low level between when the reset by the
RESET pin is released and when the OCDM.OCDM0 bit is cleared (0).
For details, see 4.5.3 Cautions on on-chip debug pins.
Cautions 1. When the power is turned on, the P53 pin may output an undefined level temporarily even during
reset.
2. The P50 to P56 pins have hysteresis characteristics in the input mode of the alternate-function
pin, but do not have the hysteresis characteristics in the port mode.