Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER) R01UH0042EJ0500 Rev.5.00 Page 1248 of 1513 Aug 12, 2011
Figure 22-1. Priority of DMA (1)
Preparation
for transfer
Read Write
Idle
End
processing
DMA2
processing
CPU processing
DMA1 processing
CPU processing
CPU processing DMA0 processing
DMA0 transfer request
System clock
DMA1 transfer request
DMA2 transfer request
DMA transfer
Mode of processing
DF0 bit
DF1 bit
DF2 bit
Preparation
for transfer
Read Write
Idle
End
processing
Preparation
for transfer
Read
Remarks 1. Transfer in the order of DMA0 → DMA1 → DMA2
2. In the case of transfer between external memory spaces (multiplexed bus, no wait)