Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER)
R01UH0042EJ0500 Rev.5.00 Page 1243 of 1513
Aug 12, 2011
22.4 Transfer Targets
Table 22-2 shows the relationship between the transfer targets (√: Transfer enabled, ×: Transfer disabled).
Table 22-2. Relationship Between Transfer Targets
Transfer Destination
Internal ROM
On-Chip
Peripheral I/O
Internal RAM External Memory
On-chip peripheral I/O
× √ √ √
Internal RAM
× √ × √
External memory
× √ √ √
Source
Internal ROM
× × × ×
Caution The operation is not guaranteed for combinations of transfer destination and source marked with “×”
in Table 22-2.
22.5 Transfer Modes
Single transfer is supported as the transfer mode.
In single transfer mode, the bus is released at each byte/halfword transfer. If there is a subsequent DMA transfer
request, transfer is performed again once. This operation continues until a terminal count occurs.
When the DMAC has released the bus, if another higher priority DMA transfer request is issued, the higher priority DMA
request always takes precedence.
If a new transfer request of the same channel and a transfer request of another channel with a lower priority are
generated in a transfer cycle, DMA transfer of the channel with the lower priority is executed after the bus is released to the
CPU (the new transfer request of the same channel is ignored in the transfer cycle).