Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER)
R01UH0042EJ0500 Rev.5.00 Page 1242 of 1513
Aug 12, 2011
(7) External DMA request enable register (EXDRQEN)
The EXDRQEN register sets the DMA request to each DMA channel when connecting the external USB device by
using the UDMARQm/UDMAAKm pin (m = 0, 1).
This register can be read or written in 8-bit units.
Reset sets This register to 00H.
RQ3EX1E
RQnEX1E
0
1
Assignment of DMA channel n (n = 0 to 3)
Does not assign DMA channel n to UDMARQ1/UDMAAK1 pin
Assigns DMA channel n to UDMARQ1/UDMAAK1 pin
EXDRQEN RQ2EX1E RQ1EX1E RQ0EX1E RQ3EX0E RQ2EX0E RQ1EX0E RQ0EX0E
65
4
3
21
7
0
RQnEX0E
0
1
Assignment of DMA channel n (n = 0 to 3)
Does not assign DMA channel n to UDMARQ0/UDMAAK0 pin
Assigns DMA channel n to UDMARQ0/UDMAAK0 pin
After reset: 00H R/W Address: FFFFFF60H
Cautions 1. Assigning multiple DMA channels to the UDMARQ1/UDMAAK1 pin is prohibited (setting
the RQ3EX1E, RQ2EX1E, RQ1EX1E, and RQ0EX1E bits to the UDMARQ1/UDMAAK1 pin at
the same time is prohibited).
2. Assigning multiple DMA channels to the UDMARQ0/UDMAAK0 pin is prohibited (setting
the RQ3EX0E, RQ2EX0E, RQ1EX0E, and RQ0EX0E bits to the UDMARQ0/UDMAAK0 pin at
the same time is prohibited).
3. Assigning both the UDMARQ1/UDMAAK1 pin and the UDMARQ0/UDMAAK0 pin to the
same DMA channel is prohibited (setting the RQ3EX1E and RQ3EX0E, RQ2EX1E and
RQ2EX0E, RQ1EX1E and RQ1EX0E, and RQ0EX1E and RQ0EX0E bits respectively at the
same time is prohibited).
4. When using a DMA request from an external source by setting the EXDRQEN register, set
the DTFRn.IFCn5-IFCn0 bit to 000000 (to prohibit a DMA request via an interrupt).
For details, see 22.3 (6) DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3).