Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER)
R01UH0042EJ0500 Rev.5.00 Page 1239 of 1513
Aug 12, 2011
(6) DMA trigger factor registers 0 to 3 (DTFR0 to DTFR3)
The DTFR0 to DTFR3 registers are 8-bit registers that control the DMA transfer start trigger via interrupt request
signals from on-chip peripheral I/O.
The interrupt request signals set by these registers serve as DMA transfer start factors.
These registers can be read or written in 8-bit units. However, DFn bit can be read or written in 1-bit units.
Reset sets these registers to 00H.
DTFRn
(n = 0 to 3)
No DMA transfer request
DMA transfer request
DFn
Note
0
1
DMA transfer request status flag
After reset: 00H R/W Address: DTFR0 FFFFF810H, DTFR1 FFFFF812H,
DTFR2 FFFFF814H, DTFR3 FFFFF816H
DFn 0 IFCn5 IFCn4 IFCn3 IFCn2 IFCn1 IFCn0
0123456<7>
Note Do not set the DFn bit to 1 by software. Write 0 to this bit to clear a DMA transfer request if an interrupt
that is specified as the DMA transfer start factor occurs while DMA transfer is disabled.
Cautions 1. Set the IFCn5 to IFCn0 bits at the following timing when DMA transfer is disabled
(DCHCn.Enn bit = 0).
• Period from after reset to start of first DMA transfer
• Period from after channel initialization by DCHCn.INITn bit to start of DMA transfer
• Period from after completion of DMA transfer (DCHCn.TCn bit = 1) to start of the next
DMA transfer
2. An interrupt request that is generated in the standby mode (IDEL1, IDLE2, STOP, or sub-
IDLE mode) does not start the DMA transfer cycle (nor is the DFn bit set to 1).
3. If a DMA start factor is selected by the IFCn5 to IFCn0 bits, the DFn bit is set to 1 when an
interrupt occurs from the selected on-chip peripheral I/O, regardless of whether the DMA
transfer is enabled or disabled. If DMA is enabled in this status, DMA transfer is
immediately started.
4. Be sure to follow the steps below when changing the DTFRn register settings.
• When the values to be set to bits IFCn5 to IFCn0 are not set to bits IFCm5 to IFCm0 of
another channel (n = 0 to 3, m = 0 to 3, n ≠ m)
<1> Stop the DMAn operation of the channel to be rewritten (DCHCn.Enn bit = 0).
<2> Change the DTFRn register settings. (Be sure to set DFn bit = 0 and change the
settings in the 8-bit manipulation.)
<3> Confirm that DFn bit = 0. (Stop the interrupt generation source operation
beforehand.)
<4> Enable the DMAn operation (Enn bit = 1).
• When the values to be set to bits IFCn5 to IFCn0 are set to bits IFCm5 to IFCm0 of
another channel (n = 0 to 3, m = 0 to 3, n ≠ m)
<1> Stop the DMAn operation of the channel to be rewritten (DCHCn.Enn bit = 0).
<2> Stop the DMAm operation of the channel where the same values are set to bits
IFCm5 to IFCm0 as the values to be used to rewrite bits IFCn5 to IFCn0
(DCHCm.Emm bit = 0).
<3> Change the DTFRn register settings. (Be sure to set DFn bit = 0 and change the
settings in the 8-bit manipulation.)
<4> Confirm that bits DFn and DFm = 0. (Stop the interrupt generation source operation
beforehand.)
<5> Enable the DMAn operation (bits Enn and Emm = 1).
Remark For the IFCn5 to IFCn0 bits, see Table 22-1 DMA Start Factors.