Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 22 DMA FUNCTION (DMA CONTROLLER)
R01UH0042EJ0500 Rev.5.00 Page 1233 of 1513
Aug 12, 2011
22.2 Configuration
CPU
Internal RAM
On-chip
peripheral I/O
On-chip peripheral I/O bus
Internal bus
Data
control
Address
control
Count
control
Channel
control
DMAC
V850ES/JG3-H, V850ES/JH3-H
Bus interface
External bus
External
RAM
External
ROM
External I/O
DMA source address
register n (DSAnH/DSAnL)
DMA transfer count
register n (DBCn)
DMA channel control
register n (DCHCn)
DMA destination address
register n (DDAnH/DDAnL)
DMA addressing control
register n (DADCn)
DMA trigger factor
register n (DTFRn)
External DMA request
enable register n (EXDRQN)
UDMARQm
UDMAAKm
Remark n = 0 to 3
m = 0, 1