Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1227 of 1513
Aug 12, 2011
21.9.7 Transmitting data for bulk transfer (IN) in DMA mode
Bulk transfer (IN) is allocated to Endpoint1 and Endpoint3. The flowchart shown below illustrates how Endpoint1 is
controlled when DMA is used. Endpoint3 can also be controlled in the same sequence. To use this flowchart as the
control flow of Endpoint3, therefore, read the bit names of Endpoint1 in the flowchart as those of Endpoint3.
If data for bulk transfer (IN) can be written by setting the DQBI1MS bit of the UF0IDR register to 1, the DMA request
signal for Endpoint1, instead of an interrupt request (INTUSBF0), becomes active. This DMA request signal for Endpoint1
operates according to the setting of the MODEn bit of the UF0IDR register (n = 0, 1). If all the data that can be written to
the UF0BI1 register has been written by DMA, the DMA request signal for Endpoint1 becomes inactive. In this status, the
toggle operation of the FIFO takes place and, if data for bulk transfer (IN) can be written, the DMA request signal for
Endpoint1 becomes active again. The automatic toggle operation of the FIFO is not executed even if the FIFO has
become full as a result of DMA transfer, unless the BKI1T bit of the UF0DEND register is set to 1. Therefore, be sure to
set the BKI1DED bit of the UF0DEND register to 1 to transfer data. If DMA is completed by the DMA end signal for
Endpoint1, the DQBI1MS bit of the UF0IDR register is cleared to 0, and the DMA request signal for Endpoint1 becomes
inactive. At the same time, the DMA_END interrupt request is issued. To transmit a short packet at this time when the
FIFO is not full, set the BKI1DED bit of the UF0DEND register to 1.
Caution The DMA request signal for Endpoint n (n = 1, 3) becomes active in the demand mode (MODE1 and
MODE0 bits of the UF0IDR register = 10), as long as data can be transferred.
(1) Initial settings for a bulk transfer (IN: EP1, EP3)
(a) Initial settings for DMAC
- The DSAn registers (n = 0 to 3) are set to 00201000H (for EP1) or 00202000H (for EP3).
- The DADCn registers (n = 0 to 3) are set to 0020H.
(8-bit transfer, transfer source address: incremental, transfer destination address: fixed)
- The DTFRn registers (n = 0 to 3) are set to 0000H.
- The UFDRQEN register is set up according to the DMA channel to be used.
(For details, see 20.6.10 (1) USBF DMA request enable register (UFDRQEN).)
(b) Initial settings for EPC
- The UF0IDR register is set to 42H (for EP1) or 82H (for EP3) (demand mode).
- The UF0IM0.DMAEDM bit = 0
- The UF0IM2.BKI1NLM bit = 0 (for EP1)
- The UF0IM2.BKI1DTM bit = 0 (for EP1)
- The UF0IM2.BKI2NLM bit = 0 (for EP3)
- The UF0IM2.BKI2DTM bit = 0 (for EP3)