Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1226 of 1513
Aug 12, 2011
Figure 21-32. DMA Processing by Bulk Transfer (OUT) (3/3)
(2)
Yes
DMA channel 2
transfer completed?
No
Moving to INTDMA2
interrupt vector
DMA channel 2 transfer
completion
TC2 = 1 (DCHC2)
DQBO1MS = 0 (UF0IDR)
Clearing DMA channel 2
transfer request
Each bit cleared by reading
UF0DMSI
TC2 bit cleared by reading
DCHC2
An interrupt occurred when
receiving Endpoint2 data.
Confirm data reception.
Cancel transfer when
NULL packet is received.
*: After setting the number of
DMA channel 2 transfers
Moving to INTUSBF0
interrupt vector
Reading UF0IS3 register
Reading UF0BO1 register
Starting transfer of
DMA channel 2
Yes
INTUSBF0 interrupt occurred?
No
Yes
BKO1DT = 1 (UF0IS3)?
No
Yes
BKO1NL = 1?
(UF0IS3)
No
Setting DMA channel 2
DBC2L = UF0BO1L − 1*
E22 = 1 (DCHC2)
DQBO1MS = 1 (UF0IDR)
(4)
(4)
Remarks 1. The above flowchart shows the case where the transfer by DMA channel 2 is from Endpoint2 to
internal data RAM, and the transfer by DMA channel 3 is from internal data RAM to Endpoint1.
2. n = 0, 1
m = 2, 3
3. ♦: Processing by hardware