Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1225 of 1513
Aug 12, 2011
Figure 21-32. DMA Processing by Bulk Transfer (OUT) (2/3)
(3)
Yes
The number of
DMA channel 3 transfers has
been changed?
No
Moving to INTDMA3
interrupt vector
Changing the set value
of DBC3L register
(1)
(3)
DMA channel 3 transfer
completion
TC3 = 1 (DCHC3)
DQBI1MS = 0 (UF0IDR)
Clearing DMA channel 3
transfer request
*: Re-set DMA channel 3
Setting DMA channel 3
E33 = 1 (DCHC3)
DQBI1MS = 1 (UF0IDR)*
Each bit cleared by reading
UF0DMSI
TC3 bit cleared by reading
DCHC3
Remarks 1. The above flowchart shows the case where the transfer by DMA channel 2 is from Endpoint2 to
internal data RAM, and the transfer by DMA channel 3 is from internal data RAM to Endpoint1.
2. n = 0, 1
3. ♦: Processing by hardware