Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1224 of 1513
Aug 12, 2011
Figure 21-32. DMA Processing by Bulk Transfer (OUT) (1/3)
START
Setting DMA channel 2
Setting address (DDA2) of
transfer destination
(internal data RAM)
Setting address (DSA2) of
transfer source
(Endpoint2 (UF0BO1)) DBC2
DADC2 register = 0080H
Setting DMA channel 3
Setting address (DDA3) of
transfer destination
(Endpoint1 (UF0BI1))
Setting address (DSA3) of
transfer source
(internal data RAM)
DBC3L register = 003FH*
DADC3 register = 0020H
(4)
(3)
*: When transferring less than 64 bytes,
change the set value.
*: Release the mask setting of the
necessary interrupts
Yes
Transfer of DMA channel 3
is completed?
No
(2)
(1)
USB setting (DMA related)
• DMAEDM = 0 (UF0IM0)*
• BKI1NM = 0 (UF0IM2)
• BKI1DTM = 0 (UF0IM2)
• BKO1NLM = 0 (UF0IM3)
• BKO1DTM = 0 (UF0IM3)
Setting DMA channel 2
E22 = 1 (DCHC2)
DTFR2 register = 00H
The use of an interrupt
request signal as the DMA
start trigger is disabled.
DQBO1MS = 1(UF0IDR)
UF0E2DC1 = 0001H
Setting DMA channel 3
E33 = 1 (DCHC3)
DTFR3 register = 00H
The use of an interrupt
request signal as the DMA
start trigger is disabled.
DQBI1MS = 1 (UF0IDR)
UF0E1DC1 = 0001H
Specifying DMA channel
and transfer destination
endpoint using UFDRQEN
register
UF0IDR register = 02H
(setting demand mode)
Remarks 1. The above flowchart shows the case where the transfer by DMA channel 2 is from Endpoint2 to
internal data RAM, and the transfer by DMA channel 3 is from internal data RAM to Endpoint1.
2. ♦: Processing by hardware