Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1183 of 1513
Aug 12, 2011
Table 21-8. Register Values in Specific Status (2/2)
Register Name After CPU Reset (RESET) After Bus Reset
UF0E3IM register 00H Value is held.
UF0E4IM register 00H Value is held.
UF0E7IM register 00H Value is held.
UF0E0R register Undefined
Note 1
Value is held.
UF0E0L register 00H Value is held.
UF0E0ST register 00H 00H
UF0E0W register Undefined
Note 1
Value is held.
UF0BO1 register Undefined
Note 1
Value is held.
UF0BO1L register 00H Value is held.
UF0BO2 register Undefined
Note 1
Value is held.
UF0BO2L register 00H Value is held.
UF0BI1 register Undefined
Note 1
Value is held.
UF0BI2 register Undefined
Note 1
Value is held.
UF0INT1 register Undefined Value is held.
UF0DSTL register 00H 00H
UF0E0SL register 00H 00H
UF0E1SL register 00H 00H
UF0E2SL register 00H 00H
UF0E3SL register 00H 00H
UF0E4SL register 00H 00H
UF0E7SL register 00H 00H
UF0ADRS register 00H 00H
UF0CNF register 00H 00H
UF0IF0 register 00H 00H
UF0IF1 register 00H 00H
UF0IF2 register 00H 00H
UF0IF3 register 00H 00H
UF0IF4 register 00H 00H
UF0DSCL register 00H Value is held.
UF0DDn register (n = 0 to 17) Note 2 Note 2
UF0CIEn register (n = 0 to 255) Note 2 Note 2
Notes 1. This register can be cleared to 0 by the RESET signal because its write pointer, counter, and read pointer
are cleared to 0 when the RESET signal becomes active, in the same manner as clearing by the UF0FICn
register, as the register is controlled by FIFO.
2. This register cannot be cleared to 0. Because data can be written to it by FW, however, any value can be
written to the register (before doing so, however, be sure to set the EP0NKA bit of the UF0E0NA register to
1).