Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1177 of 1513
Aug 12, 2011
21.6.10 Peripheral control registers
(1) USBF DMA request enable register (UFDRQEN)
The UFDRQEN register specifies the DMA channel to be used and the endpoint to be transferred.
The UFDRQEN register can be read or written in 8-bit or 16-bit units.
(1/2)
After reset: 0000H R/W Address: 00240000H
15 14 13 12 11 10 9 8
UFDRQEN RQ3UR3E RQ2UR3E RQ1UR3E RQ0UR3E RQ3UR2E RQ2UR2E RQ1UR2E RQ0UR2E
7 6 5 4 3 2 1 0
RQ3UR1E RQ2UR1E RQ1UR1E RQ0UR1E RQ3UR0E RQ2UR0E RQ1UR0E RQ0UR0E
Bit position Bit name Function
15, 11, 7, 3
RQ3UR3E,
RQ3UR2E,
RQ3UR1E,
RQ3UR0E
Specify the endpoint n (EPn) to be transferred by DMA channel 3.
(n = 1 to 4)
RQ3UR3E RQ3UR2E RQ3UR1E RQ3UR0E EP transferred by DMA3
1 0 0 0 EP4
0 1 0 0 EP3
0 0 1 0 EP2
0 0 0 1 EP1
Other than above
DMA3 does not transfer EPn
(DMA3 not used)
14, 10, 6, 2
RQ2UR3E,
RQ2UR2E,
RQ2UR1E,
RQ2UR0E
Specify the endpoint n (EPn) to be transferred by DMA channel 2.
(n = 1 to 4)
RQ2UR3E RQ2UR2E RQ2UR1E RQ2UR0E EP transferred by DMA2
1 0 0 0 EP4
0 1 0 0 EP3
0 0 1 0 EP2
0 0 0 1 EP1
Other than above
DMA2 does not transfer EPn
(DMA2 not used)