Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1169 of 1513
Aug 12, 2011
(4) CPU I/F bus control register (CPUBCTL)
The CPUBCTL register controls the interface between bridge circuit and CPU.
The CPUBCTL register can be read or written in 16-bit units.
After reset: Undefined R/W Address: 00200408H
15 14 13 12 11 10 9 8
CPUBCTL 0 0 0 0 0 0 0 0
7 6 5 4 3 2 1 0
0 0 0 0 0 BULKWAIT DATAWAIT NOWAIT
Bit position Bit name Function
2 BULKWAIT
Forcibly inserting the 1 wait (bulk wait) when the bulk register is accessed.
0: No forcibly insert the bulk wait
Note
(default value)
1: Forcibly insert the bulk wait
Note The setting is invalid in write accessing, the bulk wait is forcibly inserted.
1 DATAWAIT
Forcibly inserting the 1 wait (data wait) after the CPU bus cycle.
0: No forcibly insert the data wait (default value)
1: Forcibly insert the data wait
0 NOWAIT
Setting enables/disable the no wait operation of CPU bus cycle.
0: No wait disables
Note
(default value)
1: No wait enables
Note 1 wait or more is inserted.