Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1166 of 1513
Aug 12, 2011
21.6.6 Bridge register
(1) Bridge interrupt control register (BRGINTT)
The BRGINTT register controls the DMA transfer status of the interrupt generate status, and each end point (EP1
to EP4) from EPC to bridge circuit.
The BRGINTT register can be read or written in 16-bit units.
After reset: 0000H R/W Address: 00200400H
15 14 13 12 11 10 9 8
BRGINTT 0 0 0 0 EP4INT EP3INT EP2INT EP1INT
7 6 5 4 3 2 1 0
0 0 0 0 0 EPCINT2B EPCINT1B EPCINT0B
Bit position Bit name Function
11 EP4INT
In EP4, when the DMA transfer is normal terminate, or the error finished in the DMA
transferring, this bit is setting. Clearing to “0” by writing “1”.
0: DMA transfer not completion
1: DMA transfer completion
10 EP3NT
In EP3, when the DMA transfer is normal terminate, or the error finished in the DMA
transferring, this bit is setting. Clearing to “0” by writing “1”.
0: DMA transfer not completion
1: DMA transfer completion
9 EP2NT
In EP2, when the DMA transfer is normal terminate, or the error finished in the DMA
transferring, this bit is setting. Clearing to “0” by writing “1”.
0: DMA transfer not completion
1: DMA transfer completion
8 EP1NT
In EP1, when the DMA transfer is normal terminate, or the error finished in the DMA
transferring, this bit is setting. Clearing to “0” by writing “1”.
0: DMA transfer not completion
1: DMA transfer completion
2 EPCINT2B
Showing the status of the interrupt signal “EPC_INT2B” from EPC.
Clear controlling from the request of EPC register
0: Interrupt not issued
1: Interrupt issued
1 EPCINT1B
Showing the status of the interrupt signal “EPC_INT1B” from EPC.
Clear controlling from the request of EPC register
0: Interrupt not issued
1: Interrupt issued
0 EPCINT0B
Showing the status of the interrupt signal ”EPC_INT0B” from EPC.
Clear controlling from the request of EPC register
0: Interrupt not issued
1: Interrupt issued