Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1141 of 1513
Aug 12, 2011
(8) UF0 bulk-out 2 length register (UF0BO2L)
The UF0BO2L register stores the length of the data held by the UF0BO2 register.
This register is read-only, in 8-bit units. A write access to this register is ignored.
The UF0BO2L register always updates the received data length while it is receiving data. If the final transfer is
abnormal reception, the UF0BO2L register is cleared to 00H, and an interrupt request is not generated. Only if the
reception is normal, the interrupt request is generated, and FW can read as much data from the UF0BO2 register
as the value read from the UF0BO2L register. The value of the UF0BO2L register is decremented each time the
UF0BO2 register has been read.
BKO2L7UF0BO2L BKO2L6
5
BKO2L5 BKO2L4
3
BKO2L3
2
BKO2L2
1
BKO2L1 BKO2L0
Address
0020010EH
After reset
00H
0467
Bit position Bit name Function
7 to 0
BKO2L7 to
BKO2L0
These bits store the length of the data held by the UF0BO2 register.
(9) UF0 bulk-in 1 register (UF0BI1)
The UF0BI1 register is a 64-byte × 2 FIFO that stores data for Endpoint1. This register consists of two banks of 64-
byte FIFOs each of which performs a toggle operation and repeatedly connects the buses on the SIE and CPU
sides. The toggle operation takes place when no data is in the FIFO on the SIE side (counter value = 0) and when
the FIFO on the CPU side is correctly written (FIFO full or BKI1DED bit = 1).
This register is write-only, in 8-bit units. When this register is read, 00H is read.
The hardware transmits data to the USB bus in synchronization with the IN token for Endpoint1 only when the
BKI1NK bit of the UF0EN register is set to 1 (when NAK is not transmitted). The address at which data is to be
written or read is managed by the hardware. Therefore, FW can transmit data to the host only by writing the data to
the UF0BI1 register sequentially. A short packet is transmitted when data is written to the UF0BI1 register and the
BKI1DED bit of the UF0DEND register is set to 1 (BKIN1 bit of UF0EPS0 register = 1 (data exists)). A Null packet
is transmitted when the UF0BI1 register is cleared and the BKI1DED bit of the UF0DEND register is set to 1
(BKIN1 bit of the UF0EPS0 register = 1 (data exists)). When the data is transmitted correctly, a FIFO toggle
operation occurs. The BKI1DT bit of the UF0IS2 register is set to 1, and an interrupt request is generated for the
CPU. An interrupt request or DMA request can be selected by using the DQBI1MS bit of the UF0IDR register.
BKI17UF0BI1 BKI16
5
BKI15 BKI14
3
BKI13
2
BKI12
1
BKI11 BKI10
Address
00200110H
After reset
Undefined
0467
Bit position Bit name Function
7 to 0 BKI17 to BKI10 These bits store data for Endpoint1.
The operation of the UF0BI1 register is illustrated below.