Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1133 of 1513
Aug 12, 2011
Figure 21-6. Operation of UF0E0W Register
(a) 16-byte transmission
Status of
UF0E0W register
Trans-
mission
starts
Trans-
mission
completed
ACK
reception
Trans-
mission
starts
Trans-
mission
completed
Re-
trans-
mission
starts
ACK
reception
ACK
cannot be
received
EP0NKW bit of
UF0E0N register
EP0W bit of
UF0EPS0 register
E0INDT bit of
UF0IS1 register
FIFO full
Hardware
clear
Hardware
clear
Hardware clear
FIFO full
16-byte transfer16-byte transfer Re-transfer
INT clear
(FW clear)
Writing
FIFO
starts
Writing
FIFO
completed
Writing
FIFO
starts
Writing
FIFO
completed
Counter
reloaded
(b) When Null packet or short packet is transmitted
Status of
UF0E0W register
Transmission
starts
Trans-
mission
completed
ACK
reception
Transmission
starts
Trans-
mission
completed
ACK
reception
EP0NKW bit of
UF0E0N register
EP0W bit of
UF0EPS0 register
E0INDT bit of
UF0IS1 register
Hardware clear
E0DED bit of
UF0DEND
register is set.
E0DED bit of
UF0DEND
register is set.
Hardware
clear
Hardware
clear
Short packet transferTransfer of Null packet
INT clear
(FW clear)
Writing
FIFO
starts
Writing
FIFO
completed
FIFO FW
clear