Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1132 of 1513
Aug 12, 2011
(4) UF0 EP0 write register (UF0E0W)
The UF0E0W register is a 64-byte FIFO that stores the IN data (passes it to SIE) sent to the host in the data stage
to Endpoint0.
This register is write-only, in 8-bit units. When this register is read, 00H is read.
The hardware transmits data to the USB bus in synchronization with an IN token only when the EP0NKW bit of the
UF0E0N register is set to 1 (when NAK is not transmitted). When data is transmitted and when the host correctly
receives the data, the EP0NKW bit of the UF0E0N register is automatically cleared to 0 by hardware. A short
packet is transmitted when data is written to the UF0E0W register and the E0DED bit of the UF0DEND register is
set to 1 (EP0W bit of the UF0EPS0 register = 1 (data exists)). A Null packet is transmitted when the UF0E0W
register is cleared and the E0DED bit of the UF0DEND register is set to 1 (EP0W bit of the UF0EPS0 register = 1
(data exists)).
The UF0E0W register is cleared to 0 when the next SETUP token is received while transmission has not been
completed yet. If the stage of control transfer (read) changes to the status stage while ACK has not been correctly
received in the data stage, the UF0E0W register is automatically cleared to 0. At the same time, it is also cleared
to 0 if the EP0NKW bit of the UF0E0N register is 1.
If the UF0E0W register is read while no data is in it, 00H is read.
E0W7UF0E0W E0W6
5
E0W5 E0W4
3
E0W3
2
E0W2
1
E0W1 E0W0
Address
00200106H
After reset
Undefined
0467
Bit position Bit name Function
7 to 0 E0W7 to E0W0 These bits store the IN data sent to the host in the data stage to Endpoint0.
The operation of the UF0E0W register is illustrated below.