Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1131 of 1513
Aug 12, 2011
Figure 21-5. Operation of UF0E0ST Register
(a) Normal
Status of
UF0E0ST register
Completion of
normal reception of
SETUP token
Completion of
normal reception of
SETUP token
CPUDEC bit of
UF0IS1 register
PROT bit of
UF0IS1 register
Hardware clear
FW processing
INT clear
(FW clear)
Completion
of decoding
request
Completion
of reading
FIFO
Completion
of decoding
request
Start
of reading
FIFO
INT clear
(FW clear)
Hardware processing
(b) When SETUP transaction is received more than once
Status of
UF0E0ST register
Completion of
normal reception of
SETUP token
Start of
reception
of second
SETUP token
Completion
of normal
reception
of second
SETUP token
CPUDEC bit of
UF0IS1 register
PROT bit of
UF0IS1 register
Hardware
clear
INT clear
(FW clear)
INT clear
(FW clear)
Completion of
decoding request
Completion of
decoding request
Completion of
reading FIFO
Hardware clear
on completion of
reading 8 bytes