Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1129 of 1513
Aug 12, 2011
Figure 21-4. Operation of UF0E0R Register
Status of UF0E0R
register
Normal
completion
of reception
Normal
completion
of reception
Abnormal
reception
FIFO
hard-
ware
clear
EP0NKR bit of
UF0E0N register
EP0R bit of
UF0EPS0 register
E0ODT bit of
UF0IS1 register
Hardware clear
Hardware clear
Hardware clear
Reading
FIFO
starts
Reading
FIFO
completed
(2) UF0 EP0 length register (UF0E0L)
The UF0E0L register stores the data length held by the UF0E0R register.
This register is read-only, in 8-bit units. A write access to this register is ignored.
The UF0E0L register always updates the length of the received data while it is receiving data. If the final transfer is
abnormal reception, the UF0E0L register is cleared to 0 and the interrupt request is not generated. The interrupt
request is generated only when the reception is normal, and the FW can read as many data from the UF0E0R
register as the value read from the UF0E0L register. The value of the UF0E0L register is decremented each time
the UF0E0R register has been read.
E0L7UF0E0L E0L6
5
E0L5 E0L4
3
E0L3
2
E0L2
1
E0L1 E0L0
Address
00200102H
After reset
00H
0467
Bit position Bit name Function
7 to 0 E0L7 to E0L0 These bits store the data length held by the UF0E0R register.