Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1118 of 1513
Aug 12, 2011
(33) UF0 mode control register (UF0MODC)
This register controls CPUDEC processing.
This register can be read or written in 8-bit units.
By setting each bit of this register, the setting of the UF0MODS register can be changed. The bit of this register is
automatically cleared to 0 only at hardware reset and when the MRST bit of the UF0GRP register has been set to
1.
Even if the bit of this register has automatically been set to 1 by hardware, the setting by FW takes precedence.
Be sure to clear bits 7 and 5 to 2 to “0”. If they are set to 1, the operation is not guaranteed.
Caution This register is provided for debugging purposes. Usually, do not set this register except for
verifying the operation or when a special mode is used.
UF0MODC
5
0
3
0
2
0
1
0
Address
00200074H
After reset
00H
0
0
4
0
6
CDC
GDST
7
0
Bit position Bit name Function
6 CDCGDST
Set this bit to 1 to switch the GET_DESCRIPTOR Configuration request to CPUDEC
processing. By setting this bit to 1, the CDCGD bit of the UF0MODS register can be
forcibly set to 1.
1: Forcibly change the GET_DESCRIPTOR Configuration request to CPUDEC
processing (sets the CDCGD bit of the UF0MODS register to 1).
0: Automatically process the GET_DESCRIPTOR Configuration request (default
value).