Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1113 of 1513
Aug 12, 2011
(29) UF0 FIFO clear 0 register (UF0FIC0)
This register clears each FIFO.
This register is write-only, in 8-bit units. If this register is read, 00H is read.
FW can clear the target FIFO by writing 1 to the corresponding bit of this register. The bit to which 1 has been
written is automatically cleared to 0. Writing 0 to the bit is invalid.
The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1, 3, 7)
and the current setting of the interface.
BKI2SCUF0FIC0 BKI2CC
5
BKI1SC BKI1CC
3
ITR2C
2
ITR1C
1
EP0WC EP0RC
Address
00200060H
After reset
00H
0467
Bit position Bit name Function
7, 5 BKInSC
These bits clear only the FIFO on the SIE side of the UF0BIn register (reset the counter).
1: Clear
Writing these bits is invalid while an IN token for Endpoint m is being processed with the
BKInNK bit set to 1.
The BKInNK bit is automatically cleared to 0 by clearing the FIFO. Make sure that the
FIFO on the CPU side is empty when these bits are used.
6, 4 BKInCC
These bits clear only the FIFO on the CPU side of the UF0BIn register (reset the counter).
1: Clear
2 ITR1C
These bits clear the UF0INT1 register (reset the counter).
1: Clear
Writing these bits is invalid while an IN token for Endpoint 7 is being processed with the
IT1NK bit set to 1.
The IT1NK bit is automatically cleared to 0 by clearing the FIFO.
1 EP0WC
This bit clears the UF0E0W register (resets the counter).
1: Clear
Writing this bit is invalid while an IN token for Endpoint0 is being processed with the
EP0NKW bit set to 1.
The EP0NKW bit is automatically cleared to 0 by clearing the FIFO.
0 EP0RC
This bit clears the UF0E0R register (resets the counter).
1: Clear
When the EP0NKR bit is set to 1 (except when it has been set by FW), the EP0NKR bit is
automatically cleared to 0 by clearing the FIFO.
Remark n = 1, 2
m = 1 where n = 1
m = 3 where n = 2