Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1112 of 1513
Aug 12, 2011
(28) UF0 DMA status 1 register (UF0DMS1)
This register indicates the DMA status of Endpoint1 to Endpoint4.
This register is read-only, in 8-bit units.
The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4)
and the current setting of the interface.
Each bit is automatically cleared to 0 when this register is read. Even when this register is read, however, bits 4
and 3 of the UF0IS0 register are not cleared to 0. If the target endpoint is no longer supported by the
SET_INTERFACE request, each bit is automatically cleared to 0 by hardware (however, the DMA_END interrupt
request and Short interrupt request are not cleared).
DEDE4UF0DMS1 DSPE4
5
DEDE3 DEDE2
3
DSPE2
2
DEDE1
1
00
Address
00200050H
After reset
00H
0467
Bit position Bit name Function
7, 5, 4, 2 DEDEn
These bits indicate that the DMA end (TC) signal for Endpoint n becomes active and DMA
is stopped while a DMA read request is being issued from Endpoint n to memory.
1: DMA end signal for Endpoint n is active.
0: DMA end signal for Endpoint n is inactive (default value).
6, 3 DSPEm
These bits indicate that, although a DMA read request was being issued from Endpoint m
to memory, DMA has been stopped because the received data is a short packet and there
is no more data to be transferred.
1: DMASTOP_EPm signal is active.
0: DMASTOP_EPm signal is inactive (default value).
Remark n = 1 to 4
m = 2, 4