Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1111 of 1513
Aug 12, 2011
(27) UF0 DMA status 0 register (UF0DMS0)
This register indicates the DMA status of Endpoint1 to Endpoint4.
This register is read-only, in 8-bit units.
The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4)
and the current setting of the interface.
0UF0DMS0 0
5
DQE4 DQE3
3
DQE2
2
DQE1
1
00
Address
0020004EH
After reset
00H
0467
Bit position Bit name Function
5 DQE4
This bit indicates that a DMA read request is being issued from Endpoint4 to memory.
1: DMA read request from Endpoint4 is being issued.
0: DMA read request from Endpoint4 is not being issued (default value).
4 DQE3
This bit indicates that a DMA write request is being issued from memory to Endpoint3.
Note that, even if data is in Endpoint3 (when the FIFO is not full and after the BKI2DED
bit has been set to 1), the DMA request signal becomes active immediately and DMA
transfer is started when the DQBI2MS bit of the UF0IDR register is set to 1.
1: DMA write request for Endpoint3 is being issued.
0: DMA write request for Endpoint3 is not being issued (default value).
3 DQE2
This bit indicates that a DMA read request is being issued from Endpoint2 to memory.
1: DMA read request from Endpoint2 is being issued.
0: DMA read request from Endpoint2 is not being issued (default value).
2 DQE1
This bit indicates that a DMA write request is being issued from memory to Endpoint1.
Note that, even if data is in Endpoint1 (when the FIFO is not full and after the BKI1DED
bit has been set to 1), the DMA request signal becomes active immediately and DMA
transfer is started when the DQBI1MS bit of the UF0IDR register is set to 1.
1: DMA write request for Endpoint1 is being issued.
0: DMA write request for Endpoint1 is not being issued (default value).