Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1105 of 1513
Aug 12, 2011
(22) UF0 INT clear 1 register (UF0IC1)
This register controls clearing the interrupt sources indicated by the UF0IS1 register.
This register is write-only, in 8-bit units. If this register is read, the value FFH is read.
FW can clear an interrupt source by writing 0 to the corresponding bit of this register. Even a bit that is
automatically cleared to 0 by hardware can be cleared by FW before it is cleared by hardware. Writing 0 to a bit of
this register automatically sets the bit to 1. Writing 1 is invalid.
UF0IC1
5
E0
INDTC
3
SUCESC
2
STGC
1
PROTC CPU
DECC
Address
0020003EH
After reset
FFH
04
E0ODTC
6
E0INC
7
1
Bit position Bit name Function
6 E0INC
This bit clears the EP0IN interrupt.
0: Clear
5 E0INDTC
This bit clears the EP0INDT interrupt.
0: Clear
4 E0ODTC
This bit clears the EP0OUTDT interrupt.
0: Clear
3 SUCESC
This bit clears the Success interrupt.
0: Clear
2 STGC
This bit clears the Stg interrupt.
0: Clear
1 PROTC
This bit clears the Protect interrupt.
0: Clear
0 CPUDECC
This bit clears the CPUDEC interrupt.
0: Clear