Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1104 of 1513
Aug 12, 2011
(21) UF0 INT clear 0 register (UF0IC0)
This register controls clearing the interrupt sources indicated by the UF0IS0 register.
This register is write-only, in 8-bit units. If this register is read, the value FFH is read.
FW can clear an interrupt source by writing 0 to the corresponding bit of this register. Even a bit that is
automatically cleared to 0 by hardware can be cleared by FW before it is cleared by hardware. Writing 0 to a bit of
this register automatically sets the bit to 1. Writing 1 is invalid.
BUS
RSTC
UF0IC0
RSU
SPDC
5
1
3
DMA
EDC
2
SET
RQC
1
CLR
RQC
EP
HALTC
Address
0020003CH
After reset
FFH
04
SHORTC
67
Bit position Bit name Function
7 BUSRSTC
This bit clears the Bus Reset interrupt.
0: Clear
6 RSUSPDC
This bit clears the Resume/Suspend interrupt.
0: Clear
4 SHORTC
This bit clears the Short interrupt.
0: Clear
3 DMAEDC
This bit clears the DMA_END interrupt.
0: Clear
2 SETRQC
This bit clears the SET_RQ interrupt.
0: Clear
1 CLRRQC
This bit clears the CLR_RQ interrupt.
0: Clear
0 EPHALTC
This bit clears the EP_Halt interrupt.
0: Clear