Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1100 of 1513
Aug 12, 2011
(17) UF0 INT mask 1 register (UF0IM1)
This register controls masking of the interrupt sources indicated by the UF0IS1 register.
This register can be read or written in 8-bit units.
FW can mask occurrence of an interrupt request from USBF (INTUSBF0) by writing 1 to the corresponding bit of
this register.
UF0IM1
5
E0
INDTM
3
SUCESM
2
STGM
1
PROTM CPU
DECM
Address
00200030H
After reset
00H
04
E0
ODTM
6
E0INM
7
0
Bit position Bit name Function
6 E0INM
This bit masks the EP0IN interrupt.
1: Mask
0: Do not mask (default value)
5 E0INDTM
This bit masks the EP0INDT interrupt.
1: Mask
0: Do not mask (default value)
4 E0ODTM
This bit masks the EP0OUTDT interrupt.
1: Mask
0: Do not mask (default value)
3 SUCESM
This bit masks the Success interrupt.
1: Mask
0: Do not mask (default value)
2 STGM
This bit masks the Stg interrupt.
1: Mask
0: Do not mask (default value)
1 PROTM
This bit masks the Protect interrupt.
1: Mask
0: Do not mask (default value)
0 CPUDECM
This bit masks the CPUDEC interrupt.
1: Mask
0: Do not mask (default value)