Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1099 of 1513
Aug 12, 2011
(16) UF0 INT mask 0 register (UF0IM0)
This register controls masking of the interrupt sources indicated by the UF0IS0 register.
This register can be read or written in 8-bit units.
FW can mask occurrence of an interrupt request from USBF (INTUSBF0) by writing 1 to the corresponding bit of
this register.
BUS
RSTM
UF0IM0
RSU
SPDM
5
0
3
DMA
EDM
2
SET
RQM
1
CLR
RQM
EP
HALTM
Address
0020002EH
After reset
00H
04
SHORTM
67
Bit position Bit name Function
7 BUSRSTM
This bit masks the Bus Reset interrupt.
1: Mask
0: Do not mask (default value)
6 RSUSPDM
This bit masks the Resume/Suspend interrupt.
1: Mask
0: Do not mask (default value)
4 SHORTM
This bit masks the Short interrupt.
1: Mask
0: Do not mask (default value)
3 DMAEDM
This bit masks the DMA_END interrupt.
1: Mask
0: Do not mask (default value)
2 SETRQM
This bit masks the SET_RQ interrupt.
1: Mask
0: Do not mask (default value)
1 CLRRQM
This bit masks the CLR_RQ interrupt.
1: Mask
0: Do not mask (default value)
0 EPHALTM
This bit masks the EP_Halt interrupt.
1: Mask
0: Do not mask (default value)