Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1097 of 1513
Aug 12, 2011
(2/2)
Bit position Bit name Function
4, 0 BKOnDT
These bits indicate that data has been correctly received in the UF0BOn register
(Endpoint m).
1: Reception has been completed correctly (interrupt request is generated).
0: Reception has not been completed (default value).
These bits are automatically set to 1 by hardware when data has been correctly received
and the FIFO has been toggled. At the same time, the corresponding bits of the
UF0EPS0 register are also set to 1. They are not set to 1 when the data is a Null packet.
These bits are automatically cleared to 0 by hardware when the value of the UF0BOnL
register becomes 0 as a result of reading the UF0BOn register by FW.
These bits are automatically cleared to 0 when all the contents of the FIFO on the CPU
side have been read. However, the interrupt request is not cleared if data is in the FIFO
on the SIE side at this time, and the INTUSBF1 signal does not become inactive. The
signal is kept active if data is successively received.
Remark n = 1, 2
m = 2 where n = 1
m = 4 where n = 2