Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1095 of 1513
Aug 12, 2011
(13) UF0 INT status 2 register (UF0IS2)
This register indicates the interrupt source. If the contents of this register are changed, the EPCINT1B signal
becomes active.
This register is read-only, in 8-bit units.
If an interrupt request (INTUSBF0) is generated from USBF, the FW must read this register to identify the interrupt
source.
Each bit of this register is forcibly cleared to 0 when 0 is written to the corresponding bit of the UF0IC2 register.
The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1, 3, 7)
and the current setting of the interface.
BKI2INUF0IS2 BKI2DT
5
BKI1IN BKI1DT
3
0
2
0
1
0 IT1DT
Address
00200024H
After reset
00H
0467
Bit position Bit name Function
7, 5 BKInIN
These bits indicate that an IN token has been received in the UF0BIn register (Endpoint
m) and that NAK has been returned.
1: IN token is received and NAK is transmitted (interrupt request is generated).
0: IN token is not received (default value).
6, 4 BKInDT
These bits indicate that the FIFO of the UF0BIn register (Endpoint m) has been toggled.
This means that data can be written to Endpoint m.
1: FIFO has been toggled (interrupt request is generated).
0: FIFO has not been toggled (default value).
The data written to Endpoint m is transmitted in synchronization with the IN token next to
the one that set the BKInNK bit of the UF0EN register to 1. When the FIFO has been
toggled and then data can be written from the CPU, this bit is automatically set to 1 by
hardware. It is also set to 1 when the FIFO has been toggled, even if the data is a Null
packet. This bit is automatically cleared to 0 by hardware when the first write access is
made to the UF0BIn register.
0 IT1DT
These bits indicate that data has been correctly received from the UF0INT1 register
(Endpoint x).
1: Transmission is completed (interrupt request is generated).
0: Transmission is not completed (default value).
Data is transmitted in synchronization with the IN token next to the one that set the ITnNK
bit of the UF0EN register to 1. This bit is automatically set to 1 by hardware when the
host has correctly received that data. It is automatically cleared to 0 by hardware when
the first write access is made to the UF0INT1 register. This bit is also set to 1 even when
the data is a Null packet.
Remark n = 1, 2
m = 1 and x = 7 where n = 1
m = 3 where n = 2