Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1093 of 1513
Aug 12, 2011
(12) UF0 INT status 1 register (UF0IS1)
This register indicates the interrupt source. If the contents of this register are changed, the EPCINT0B signal
becomes active.
This register is read-only, in 8-bit units.
If an interrupt request (INTUSBF0) is generated from USBF, the FW must read this register to identify the interrupt
source.
Each bit of this register is forcibly cleared to 0 when 0 is written to the corresponding bit of the UF0IC1 register.
However, the SUCES and STG bits of the UF0IS1 register are automatically cleared to 0 when the next SETUP
token has been received.
Caution In the USBF, multiple interrupt sources, such as Bus Reset, Resume, and Short, are ORed
internally and are issued as a single interrupt request (INTUSBF0). Therefore, in the case of the
occurrence of multiple interrupt sources, they are ORed and issued as an INTUSBF0 interrupt
request.
For example, if a Bus Reset interrupt source and Resume interrupt source occur, the two
sources are ORed and an INTUSBF0 interrupt request is issued.
Under these conditions, if the Bus Reset interrupt source is cleared to 0 (UF0IC0.BUSRSTC = 0),
the V850ES/JG3-H or V850ES/JH3-H internal INTUSBF0 interrupt request may remain set to 1
since the Resume interrupt source will still be remaining. The new interrupt request flag
(US0BIC.US0BIF), therefore, might not be set to 1.
In this case, after performing clear processing for each interrupt request with the INTUSBF0
interrupt servicing routine, confirm the flag status for the UF0IS0 and UF0IS1 registers again,
and if there are any interrupt sources with flags set to 1, perform flag clearing (only the
applicable bits need to be cleared (do not perform a batch clearing)).
(1/2)
UF0IS1
CPU
DEC
5
E0INDT
3
SUCES
2
STG
1
PROT
Address
00200022H
After reset
00H
04
E0ODT
6
E0IN
7
0
Bit position Bit name Function
6 E0IN
This bit indicates that an IN token for Endpoint0 has been received and that the hardware
has automatically transmitted NAK.
1: IN token is received and NAK is transmitted (interrupt request is generated).
0: IN token is not received (default value).
5 E0INDT
This bit indicates that data has been correctly transmitted from the UF0E0W register.
1: Transmission from UF0E0W register is completed (interrupt request is generated).
0: Transmission from UF0E0W register is not completed (default value).
Data is transmitted in synchronization with the IN token next to the one that set the
EP0NKW bit of the UF0E0N register to 1. This bit is automatically set to 1 by hardware
when the host correctly receives that data. It is also set to 1 even if the data is a Null
packet. This bit is automatically cleared to 0 by hardware when the first write access is
made to the UF0E0W register.