Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1089 of 1513
Aug 12, 2011
(9) UF0 EP status 1 register (UF0EPS1)
This register indicates the USB bus status and the presence or absence of register data.
This register is read-only, in 8-bit units.
RSUMUF0EPS1 0
5
00
3
0
2
0
1
00
Address
00200010H
After reset
00H
0467
Bit position Bit name Function
7 RSUM
This bit indicates that the USB bus is in the Resume status. This bit is meaningful only
when an interrupt request is generated.
1: Suspend status
0: Resume status (default value)
Because sampling is internally performed with the clock, the operation is guaranteed only
when CLK is supplied. Care must be exercised when CLK of the system is stopped. The
INTUSBF1 signal of SIE operates even when CLK is stopped. It can therefore be
supported by making the interrupt control register (UFIC1) valid or lowering the frequency
of CLK to the USBF.
This bit is automatically cleared to 0 when it is read.