Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1081 of 1513
Aug 12, 2011
(3/4)
Bit position Bit name Function
1 BKI2NK
This bit controls NAK to Endpoint3 (bulk 2 transfer (IN)).
1: Do not transmit NAK.
0: Transmit NAK (default value).
This bit is cleared to 0 only when the FIFO connected to the SIE side of the UF0BI2
register (64-byte FIFO of bank configuration) cannot receive data. It is set to 1 when a
toggle operation is performed (the data of the UF0BI2 register is retained until
transmission has been correctly completed). The bank is changed (toggle operation)
when the following conditions are satisfied.
• Data is correctly written to the FIFO connected to the CPU bus side (writing has
been completed and the FIFO is full or the UF0DEND register is set).
• The value of the FIFO counter connected to the SIE side is 0.
This bit is automatically set to 1 and data transmission is started when the FIFO on the
CPU side becomes full and a FIFO toggle operation is performed as a result of writing
data to the FIFO. However, if the FIFO on the CPU side becomes full as a result of writing
data to it by DMA while the BKI2T bit of the UF0DEND register is cleared to 0, the toggle
operation is not performed because the condition of the toggle operation is not satisfied
until the BKI2DED bit of the UF0DEND register is set to 1. To send a short packet that
does not make the FIFO on the CPU side full, set the BKI2DED bit to 1 after completing
writing data. When the BKI2DED bit is set to 1, a toggle operation is performed and at the
same time, this bit is automatically set to 1. This bit is also cleared to 0 as soon as the
UF0BI2 register has been cleared.
Cautions 1. If DMA is enabled while data is being written to the UF0BI2 register in the PIO mode, a DMA
request is immediately issued.
2. If 64-byte data is written in the DMA transfer mode, the DMA request signal becomes
inactive. If the BKI2NK bit is then set to 1, data is transmitted in synchronization with an IN
token. The DMA request signal becomes active again as long as the DMA request is not
masked as soon as the FIFO is toggled. If the BKI2NK bit is not set, data is not transmitted
even if an IN token has been received. In this case, set the BKI2DED bit of the UF0DEND
register to 1.
3. If the TC signal is received in the DMA transfer mode, the DMA request signal becomes
inactive. At the same time, the DMA request is masked. If the BKI2NK bit is not set to 1,
data is not transmitted even if an IN token is received. When the BKI2DED bit of the
UF0DEND register is set to 1 by FW, data is transmitted in synchronization with the IN
token. To execute DMA transfer again, unmask the DMA request.