Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1080 of 1513
Aug 12, 2011
(2/4)
Bit position Bit name Function
3 BKO2NK
This bit controls NAK to Endpoint4 (bulk 2 transfer (OUT)).
1: Transmit NAK.
0: Do not transmit NAK (default value).
This bit is set to 1 only when the FIFO connected to the SIE side of the UF0BO2 register
(64-byte FIFO of bank configuration) cannot receive data. It is cleared to 0 when a toggle
operation is performed. The bank is changed (toggle operation) when the following
conditions are satisfied.
• Data correctly received is stored in the FIFO connected to the SIE side.
• The value of the FIFO counter connected to the CPU side is 0 (completion of
reading).
FW should be used to read data of the UF0BO2L register when it has received the
BLKO2DT interrupt request and read as many data from the UF0BO2 register as the
value of that data. To not receive data from the USB bus for some reason even if USBF is
ready to receive data, set this bit to 1 by FW. In this case, USBF keeps transmitting NAK
until the FW clears this bit to 0. This bit is also cleared to 0 as soon as the UF0BO2
register has been cleared.
2 BKO1NK
This bit controls NAK to Endpoint2 (bulk 1 transfer (OUT)).
1: Transmit NAK.
0: Do not transmit NAK (default value).
This bit is set to 1 only when the FIFO connected to the SIE side of the UF0BO1 register
(64-byte FIFO of bank configuration) cannot receive data. It is cleared to 0 when a toggle
operation is performed. The bank is changed (toggle operation) when the following
conditions are satisfied.
• Data correctly received is stored in the FIFO connected to the SIE side.
• The value of the FIFO counter connected to the CPU side is 0 (completion of
reading).
FW should be used to read data of the UF0BO1L register when it has received the
BLKO1DT interrupt request and read as many data from the UF0BO1 register as the
value of that data. To not receive data from the USB bus for some reason even if USBF is
ready to receive data, set this bit to 1 by FW. In this case, USBF keeps transmitting NAK
until the FW clears this bit to 0. This bit is also cleared to 0 as soon as the UF0BO1
register has been cleared.
Cautions 1. If DMA is enabled while data is being read from the UF0BO2 register in the PIO mode, a
DMA request is immediately issued.
2. If the last data of the FIFO on the CPU side is read in the DMA transfer mode, the DMA
request signal becomes inactive.
3. If the TC signal is received in the DMA transfer mode, the DMA request signal becomes
inactive.