Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 21 USB FUNCTION CONTROLLER (USBF)
R01UH0042EJ0500 Rev.5.00 Page 1079 of 1513
Aug 12, 2011
(3) UF0 EPNAK register (UF0EN)
This register controls NAK of endpoints other than Endpoint0.
This register can be read or written in 8-bit units (however, bits 4, 1, and 0 can only be read).
The BKO2NK bit can be written only when the BKO2NKM bit of the UF0ENM register is 1 and the BKO1NK bit can
be written only when the BKO1NKM bit of the UF0ENM register is 1.
The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1 to 4, 7)
and the current setting of the interface.
It takes five USB clocks to reflect the status on this register after the UF0FIC0 and UF0FIC1 registers have been
set. If it is necessary to read the status correctly, therefore, separate a write signal that accesses the UF0FIC0 and
UF0FIC1 registers from a read signal that accesses the UF0EPS0, UF0EPS1, UF0EPS2, UF0E0N, and UF0EN
registers by at least four USB clocks.
While NAK is being transmitted to Endpoint0 Read, Endpoint2, and Endpoint4, a write access to the BKO1NK and
BKO2NK bits is ignored.
Be sure to clear bits 7 to 5 to “0”. If it is set to 1, the operation is not guaranteed.
(1/4)
0UF0EN 0
5
0
IT1NK
3
BKO2NK
2
BKO1NK
1
BKI2NK BKI1NK
Address
00200004H
After reset
00H
0467
Bit position Bit name Function
4 IT1NK
This bit controls NAK to Endpoint7 (interrupt 1 transfer).
It is automatically set to 1 and transmission is started when the UF0INT1 register has
become full as a result of writing data to it. To send a short packet that does not make the
FIFO full, set the IT1DEND bit of the UF0DEND register to 1. As soon as the IT1DEND
bit has been set to 1, this bit is automatically set to 1.
1: Do not transmit NAK.
0: Transmit NAK (default value).
This bit is also cleared to 0 when the UF0INT1 register has been cleared.