Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER
R01UH0042EJ0500 Rev.5.00 Page 1037 of 1513
Aug 12, 2011
Figure 20-55. Bus-off Recovery (Normal Operation Mode with ABT)
START
No
Yes
Set CCERC bit.
Set CCERC bit = 1
END
No
Yes
Access to register other
than C0CTRL and
C0GMCTRL registers.
Set C0CTRL register.
(Set OPMODE bit.)
Set C0CTRL register.
(Set OPMODE.)
Clear all TRQ bit
Note
BOFF bit = 1?
Set C0CTRL register.
(Clear OPMODE bit.)
Clear ABTTRG bit.
Set ABTTRG bit = 0
Clear ABTTRG bit = 1
Forced recovery
from bus off?
Wait for recovery
from bus off.
Note To initialize the message buffer by clearing the RDY bit before starting the bus-off recovery sequence,
clear all the TRQ bits.
Caution If a request to change the mode from the initialization mode to any operation mode is made to
execute the bus-off recovery sequence again during a bus-off recovery sequence, the receive
error counter (C0ERC.REC0 to REC6 bits) is cleared. It is therefore necessary to detect 11
contiguous recessive bits 128 times on the bus again.
Remark OPMODE: Normal operation mode, normal operation mode with ABT, receive-only mode, single-
shot mode, self-test mode