Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER
R01UH0042EJ0500 Rev.5.00 Page 1035 of 1513
Aug 12, 2011
Figure 20-53. Clear CAN Sleep/Stop Mode
START
END
Clear PSMODE1 bit.
Set PSMODE1 bit = 0
Clear PSMODE1 bit = 1
CAN stop mode
CAN sleep mode
After dominant edge
detection,
PSMODE0 bit = 0
CINTS5 bit = 1
Clear CINTS5 bit.
Clear CINTS5 bit = 1
(When CAN clock is not supplied)
CAN sleep mode release when
CAN bus becomes active
(When CAN clock is supplied
Note
)
CAN sleep mode release when
CAN bus becomes active
Clear CINTS5 bit.
Clear CINTS5 bit = 1
Clear PSMODE0 bit.
Set PSMODE0 bit = 0
Clear PSMODE0 bit = 1
Clear PSMODE0 bit.
Set PSMODE0 bit = 0
Clear PSMODE0 bit = 1
After dominant edge
detection,
PSMODE0 bit = 0/1
CINTS5 bit = 1
CAN sleep mode
release by user
Note The state in which the CAN clock is supplied means the state in which the CAN sleep mode is set
without setting any of the following CPU standby modes.
• STOP mode
• IDLE1 and IDLE2 modes
• The main clock has been stopped in subclock operation mode or sub-IDLE mode